View SIC762CD-T1-GE3_3743121.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

vishay siliconix sic762cd document number: 65727 s10-0275-rev. a, 08-feb-10 www.vishay.com 1 integrated drmos power stage description the sic762cd is an integrated solution that contains pwm optimized n-channel mosfets (high side and low side) and a full featured mosfet driver ic. the device complies with the intel drmos standard for desktop and server v core power stages. the sic762cd delivers up to 35 a continuous output current and operates from an input voltage range of 3 v to 27 v. the integrated mosfets are optimized for output voltages in the ranges of 0.8 v to 2.0 v with a nominal input voltage of 24 v. the device can also deliver very high power at 5 v output for asic applications. the sic762cd incorporates an advanced mosfet gate driver ic. this ic accepts a single pwm input from the v r controller and converts it into the high side and low side mosfet gate drive signals. the driver ic is designed to implement the skip mode (smod) function for light load efficiency improvement. adaptive dead time control also works to improve efficiency at all load points. the sic762cd has a thermal warning (thdn) that alerts the system of excessive junction temperature. the driver ic includes an enable pin, uvlo and shoot through protection. the sic762cd is optimized for high frequency buck applications. operating frequencies in excess of 1 mhz can easily be achieved. the sic762cd is packaged in vishay siliconix high performance powerpak mlp6 x 6 package. compact co-packaging of components helps to reduce stray inductance, and hence increases efficiency. ? features ? integrated gen iii mosfets and drmos compliant gate driver ic ? enables v core switching at 1 mhz ? easily achieve > 90 % efficiency in multi-phase, low output voltage solutions ? low ringing on the vswh pin reduces emi ? pin compatible with drmos 6 x 6 version 3.0 ? tri-state pwm input function prevents negative output voltage swing ? 5 v logic levels on pwm ? mosfet threshold voltage optimized for 5 v driver bias supply ? automatic skip mode operation (smod) for light load efficiency ? under-voltage lockout ? built-in bootstrap schottky diode ? adaptive deadtime and shoot through protection ? thermal shutdown warning flag ? low profile, thermally enhanced powerpak ? mlp 6 x 6 40 pin package ? halogen-free according to iec 61249-2-21 definition ? compliant to rohs directive 2002/95/ec applications ? cpu and gpu core voltage regulation ? server, computer, workstat ion, game console, graphics boards, pc sic762cd application diagramm figure 1 gate dri v er sic762cd v ci n smod dsbl# p w m thd n c g n d gl p g n d phase v s w h boot v i n gh v dr v p w m controller v i n 5 v v o
www.vishay.com 2 document number: 65727 s10-0275-rev. a, 08-feb-10 vishay siliconix sic762cd note: a. t a = 25 c and all voltages referenced to p gnd = c gnd unless otherwise noted. stresses beyond those listed under "absol ute maximum ratings" may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condi tions beyond those indicated in the operational sections of t he specifications is not implied. exposure to absolute maximum rating/condi tions for extended periods may affect device reliability. note: a. recommended operating conditions are s pecified over the entire temperature range, and all voltages referenced to p gnd = c gnd unless otherwise noted. ordering information part number package SIC762CD-T1-GE3 powerpak mlp66-40 sic762db reference board absolute maximum ratings t a = 25 c, unless otherwise noted parameter symbol min. max. unit input voltage v in - 0.3 30 v switch node voltage (dc) v sw - 0.3 30 drive input voltage v drv - 0.3 7.0 control input voltage v cin - 0.3 7.0 logic pins v pwm , v dsbl# , v thdn , v smod - 0.3 v cin + 0.3 boot voltage dc (referenced to c gnd )v bs - 0.3 33 boot to phase voltage dc v bs_ph - 0.3 7 boot to phase voltage < 200 ns - 0.3 9 ambient temperature range t a - 40 125 c maximum junction temperature t j 150 storage junction temperature t stg - 65 150 soldering peak temperature 260 recommended operating conditions parameter symbol min. typ. max. unit input voltage v in 3.0 12 24 v control input voltage v cin 4.5 5.5 drive input voltage v drv 4.5 5.5 switch node v sw_dc 12 24 thermal resistance ratings parameter symbol typ. max. unit maximum power dissipation at t pcb = 25 c p d_25c 25 w maximum power dissipation at t pcb = 100 c p d_100c 10 thermal resistance from junction to top r th_j_top 15 c/w thermal resistance from junction to pcb r th_j_pcb 5
document number: 65727 s10-0275-rev. a, 08-feb-10 www.vishay.com 3 vishay siliconix sic762cd notes: a. typical limits are establ ished by characterization and are not production tested. b. guaranteed by design. electrical specifications parameter symbol test conditions unless specified v dsbl# = v smod = 5 v, v in = 12 v, v vdrv = v vcin = 5 v, t a = 25 c min. typ. a max. unit power supplies v cin control input current i vcin v dsbl# = 0 v, no switching 21 a v dsbl# = 5 v, no switching 350 v dsbl# = 5 v, f s = 300 khz, d = 0.1 500 drive input current (dynamic) i vdrv f s = 300 khz, d = 0.1 14 18 ma f s = 1000 khz, d = 0.1 40 54 bootstrap supply bootstrap switch forward voltage v bs diode v vcin = 5 v, forward bias current 2 ma 0.60 0.75 v control inputs (pwm, dsbl#, smod) pwm rising threshold v th_pwm_r 3.5 3.9 4.2 v pwm falling threshold v th_pwm_f 0.8 1.0 1.2 pwm tristate rising threshold v th_tri_r 0.9 1.3 1.8 pwm tristate falling threshold v th_tri_f 3.4 3.7 4.0 pwm tristate rising th reshold hysteresis v hys_tri_r 280 mv pwm tristate falling threshold hysteresis v hys_tri_f 180 tristate hold-off time b t tsho 150 ns pwm input current i pwm v pwm = 5 v 250 a v pwm = 0 v - 250 smod, dsbl# logic input voltage v logic_lh rising (low to high) 2.0 v v logic_lh falling (high to low) 0.8 pull down impedance r thdn 5 k resistor pull-up to v cin 40 thdn output low v thdnl 0.04 v protection thermal warning flag set 150 c thermal warning flag clear 135 thermal warning flag hysteresis 15 under voltage lockout v cin v uvlo rising, on threshold 3.3 3.9 v under voltage lockout v cin falling, off threshold 2.3 2.95 under voltage lockout hysteresis v cin v uvlo_hyst 400 mv high side gate discharge resistor b r hs_dscrg v vdrv = v vcin = 0 v; v in = 12 v 20.2 k
www.vishay.com 4 document number: 65727 s10-0275-rev. a, 08-feb-10 vishay siliconix sic762cd note: a. min. and max. are not 100 % production tested. timing definitions note: gh is referenced to the high side source. gl is referenced to the low side source. timing specifications parameter symbol test conditions unless specified v vdrv = v vcin = v dsbl# = 5 v, v vin = 12 v, t a = 25 c min. typ. max. unit turn off propagation delay high side a t d_off_hs 25 % of pwm to 90 % of gh 10 20 35 ns rise time high side t r_hs 10 % to 90 % of gh 10 fall time high side t f_hs 90 % to 10 % of gh 8 turn off propagation delay low side a t d_off_ls 75 % of pwm to 90 % of gl 10 37 45 rise time low side t r_ls 10 % to 90 % of gl 6 fall time low side t f_ls 90 % to 10 % of gl 5 dead time rising t dead_on 10 % of gl to 10 % of gh 27 dead time falling t dead_off 10 % of gh to 10 % of gl 19 region definition symbol 1 turn off propagation delay ls t d_off_ls 2 fall time ls t f_ls 3 dead time rising t dead_on 4 rise time hs t r_hs 5 turn off propagation delay hs t d_off_hs 6 fall time hs t f_hs 7 dead time falling t dead_off 8 rise time ls t r_ls p w m gh gl s w 1234 56 7 8 10 % 90 % 10 % 90 % 75 % 25 %
document number: 65727 s10-0275-rev. a, 08-feb-10 www.vishay.com 5 vishay siliconix sic762cd sic762cd block diagram detailed operational description pwm input with tr istate function the pwm input receives the pwm control signal from the v r controller ic. the pwm input is designed to be compatible with standard controllers using two state logic (h and l) and advanced controllers that incorporate tristate logic (h, l and tristate) on the pwm output. for two state logic, the pwm input operates as follow s. when pwm is driven above v th_pwm_r the low side is turned off and the high side is turned on. when pwm input is driven below v th_pwm_f the high side turns off and the low side turns on. for tristate logic, the pwm input operates as above for driving the mosfets. however, there is an third stat e that is entered into as the pwm output of tristate compatib le controller enters its high impedance state during shut -down. the high impedance state of the controller's pwm output allows the sic762cd to pull the pwm input into the tristate region (see the tristate voltage threshold diagram below). if the pwm input stays in this region for the tristate hold-off period, t tsho , both high side and low side mosfets are turned off. this function allows the v r phase to be disabled without negative output voltage swing caused by inductor ringing and saves a schottky diode clamp. the pwm and tristate regions are separated by hysteresis to prevent false triggering. the sic762cd incorporates pwm voltage thresholds that are compatible with 5 v logic. disable (dsbl#) in the low state, the dsbl# pin shuts down the driver ic and disables both high-side and low- side mosfet. in this state, the standby current is mini mized. if dsbl# is left unconnected an internal pull-down resistor will pull the pin down to c gnd and shut down the ic. diode emulation mode (smod) skip mode when smod pin is low the diode emulation mode is enabled. this is a non-synchronous conversion mode that improves light load efficiency by reduci ng switching losses. conducted losses that occur in synchronous buck regulators when inductor current is negative are al so reduced. circuitry in the gate drive ic detects when inductor current crosses zero and automatically stops switching the low side mosfet. see smod operation diagram for additional details. this function can also be used for a pre-biased output voltage. if smod is left unconnected, an in ternal pull up resistor will pull the pin up to v cin (logic high) to disable the diode emulation function. thermal shutdown warning (thdn) the thdn pin is an open drain signal that flags the presence of excessive junction temperature. connect a maximum of 20 k to pull this pin up to v cin . an internal temperature sensor detects the junction te mperature. the temperature threshold is 150 c. when this junction temperature is exceeded the thdn flag is set. when the junction temperature drops below 135 c the device will clear the thdn signal. the sic762cd does not stop operation when the flag is set. the decision to shutdown must be made by an external thermal control function. voltage input (v in ) this is the power input to the drain of the high-side power mosfet. this pin is connected to the high power intermediate bus rail. switch node (v swh and phase) the switch node v swh is the circuit pwm regulated output. this is the output applied to t he filter circuit to deliver the figure 2 u v lo v dr v gh gl c g n d p g n d v s w h boot v i n v ci n p w m dsbl# thd n smod thermal w arning tristate p w m ast c n tl dcm detect phase
www.vishay.com 6 document number: 65727 s10-0275-rev. a, 08-feb-10 vishay siliconix sic762cd regulated high output for the buck converter. the phase pin is internally connect ed to the switch node v swh . this pin is to be used exclusively as the return pin for the boot capacitor. a 20.2 k resistor is connected between gh and phase to provide a discharge path for the hs mosfet in the event that v cin goes to zero while v in is still applied. ground connections (c gnd and p gnd ) p gnd (power ground) should be externally connected to c gnd (control signal ground). the layout of the printed circuit board should be such that the inductance separating the c gnd and p gnd should be a minimum. transient differences due to inductance effects between these two pins should not exceed 0.5 v. control and drive supp ly voltage input (v drv ,v cin ) v cin is the bias supply for the gate drive control ic. v drv is the bias supply for the gate drivers. it is recommended to separate these pins through a resistor. this creates a low pass filtering effect to avoid coupling of high frequency gate drive noise into the ic. bootstrap circuit (boot) the internal bootstrap switch and an external bootstrap capacitor form a charge pump that supplies voltage to the boot pin. an integrated boot strap diode is incorporated so that only an external capacitor is necessary to complete the bootstrap circuit. connect a boot strap capacitor with one leg tied to boot pin and t he other tied to phase pin. shoot-through protection and adaptive dead time (ast) the sic762cd has an internal adaptive logic to avoid shoot through and optimize dead time. the shoot through protection ensures that bot h high-side and low-side mosfet are not turned on the same time. the adaptive dead time control operates as follows. when pwm input goes high the ls gate starts to go low after a few ns. when this signal crosses through 1.7 v the logic to switch the hs gate on is activated. when pwm goes low the hs gate goes low. when the hs gate-to-source drive signal crosses through 1.7 v the logic to turn on the ls gate is activated. this feature helps to adjust dead time as gate transitions change with respect to output current and temperature. under voltage lockout (uvlo) during the start up cycle, the uv lo disables t he gate drive holding high-side and low-side mosfet gate low until the input voltage rail has reached a point at which the logic circuitry can be safely activated. the sic762cd also incorporates logic to clamp the gate drive signals to zero when the uvlo falling edge triggers the shutdown of the device. as an added precaution, a 20.2 k resistor is connected between gh and phase to provide a discharge path for the hs mosfet. tristate pwm voltage threshold diagram device truth table dsbl# smod pwm gh gl open xxl l l xxl l h lllh (i l > 0), l (i l 0) h lhhl h hhhl h hllh figure 3 v th_tri_f v th_p w m_r v th_tri_r v th_p w m_f p w m gh gl t tsho t tsho
vishay siliconix sic762cd document number: 65727 s10-0275-rev. a, 08-feb-10 www.vishay.com 7 smod operation diagram pin configuration figure 4 dsbl smod p w m gh gl v s w i l > 0 i l = 0 t d(o n ) t d(off) figure 5 - powerpak mlp 6 x 6 40p pin out - top view v i n p2 a g n d p1 v s w h p3 30 v s w h 29 v s w h 2 8 p g n d 27 p g n d 26 p g n d 25 p g n d 24 p g n d 23 p g n d 22 p g n d 21 p g n d 40 p w m 39 dsbl# 3 8 thd n 37 c g n d 36 gl 35 v s w h 34 v s w h 33 v s w h 32 v s w h 31 v s w h smod 1 v ci n 2 v dr v 3 boot 4 c g n d 5 gh 6 phase 7 v i n 8 v i n 9 v i n 10 20 p g n d 19 p g n d 1 8 p g n d 17 p g n d 16 p g n d 15 v s w h 14 v i n 13 v i n 12 v i n 11 v i n pin description pin number symbol description 1 smod disable low side gate operation. active low. 2v cin this will be the bias supply input for control ic (5 v). 3v drv ic bias supply and gate drive supply voltage (5 v). 4 boot high side driver bootstrap voltage pin for external bootstrap capacitor. 5, 37, pad1 c gnd control signal ground. it should be connected to p gnd externally. all pins internally connected. 6 gh gate signal output pin for high side mosfet. pin for monitoring. 7 phase return pin for the hs bootstrap capacitor. connect a 0.1 f ceramic capacitor from th is pin to the boot pin (4). 8 to 14, pad2 v in input voltage for power stage. it is the drain of the high-side mosfet. 15, 29 to 35, pa d 3 vswh it is the phase node between high side mosfet source and low side mosfet drain. it should be connected to an output inductor. all pins internally connected. 16 to 28 p gnd power ground. 36 gl gate signal output pin for low side mosfet. pin for monitoring. 38 thdn thermal shutdown open drain output. use a 10k pull up resistor to v cin . 39 dsbl# disable pin. active low. 40 pwm pwm input logic signal. compatible with tristate controller function.
www.vishay.com 8 document number: 65727 s10-0275-rev. a, 08-feb-10 vishay siliconix sic762cd electrical characteristics i cin (ma) vs. temperature at frequency = 300 khz d = 10 %, v cin = v drv = 5 v pwm falling threshold (v) vs. temperature (c) v cin = v drv = 5 v dsbl falling threshold (v) vs. temperature (c) v cin = v drv = 5 v 0.0 0.2 0.4 0.6 0. 8 1.0 - 40 - 25 - 10 5 20 35 50 65 8 095110125140 temperat u re (c) i ci n (ma) - 40 - 25 - 10 5 20 35 50 65 8 0 95 110 125 140 temperat u re (c) p w m t sh ( v ) 0. 8 0.9 1.0 1.1 1.2 1.3 - 40 - 25 - 10 5 20 35 50 65 8 0 95 110 125 140 temperat u re (c) dsbl t sh ( v ) 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 i drv (ma) vs. temperature at frequency = 300 khz d = 10 %, v cin = v drv = 5 v pwm rising threshold (v) vs. temperature (c) v cin = v drv = 5 v dsbl rising threshold (v) vs. temperature (c) v cin = v drv = 5 v - 40 - 25 - 10 5 20 35 50 65 8 0 95 110 125 140 temperat u re (c) i dr v (ma) 6 8 10 12 14 16 1 8 20 - 40 - 25 - 10 5 20 35 50 65 8 0 95 110 125 140 temperat u re (c) p w m t sh ( v ) 3.0 3.2 3.4 3.6 3. 8 4.0 4.2 4.4 - 40 - 25 - 10 5 20 35 50 65 8 0 95 110 125 140 temperat u re (c) dsbl t sh ( v ) 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1. 8 0 1.40
vishay siliconix sic762cd document number: 65727 s10-0275-rev. a, 08-feb-10 www.vishay.com 9 electrical characteristics smod falling threshold (v) vs. temperature (c) v cin = v drv = 5 v i cin + i drv (ma) vs. temperature at frequency = 1 mhz d = 10 %, v cin = v drv = 5 v pwm falling tristate (v) vs. temperature (c) v cin = v drv = 5 v - 40 - 25 - 10 5 20 35 50 65 8 0 95 110 125 140 temperat u re (c) smod t sh ( v ) 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 - 40 - 25 - 10 5 20 35 50 65 8 0 95 110 125 140 temperat u re (c) i ci n (ma) 0 10 20 30 40 50 60 - 40 - 25 - 10 5 20 35 50 65 8 0 95 110 125 140 temperat u re (c) p w m t sh ( v ) 1.0 1.1 1.2 1.3 1.4 1.5 1.6 smod rising threshold (v) vs. temperature (c) v cin = v drv = 5 v i drv (ma) vs. temperature at frequency = 1 mhz d = 10 %, v cin = v drv = 5 v pwm rising tristate threshold (v) vs. temperature (c) v cin = v drv = 5 v - 40 - 25 - 10 5 20 35 50 65 8 0 95 110 125 140 temperat u re (c) smod t sh ( v ) 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1. 8 0 - 40 - 25 - 10 5 20 35 50 65 8 0 95 110 125 140 temperat u re (c) i dr v (ma) 25 30 35 40 45 50 - 40 - 25 - 10 5 20 35 50 65 8 0 95 110 125 140 temperat u re (c) p w m t sh ( v ) 3.0 3.2 3.4 3.6 3. 8 4.0 4.2 4.4
www.vishay.com 10 document number: 65727 s10-0275-rev. a, 08-feb-10 vishay siliconix sic762cd electrical characteristics dsbl falling threshold vs. v cin smod falling threshold vs. v cin pwm falling threshold vs. v cin v ci n ( v ) dsbl t sh ( v ) 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 4.7 4. 8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6 v ci n ( v ) dsbl t sh ( v ) 4.7 4. 8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 v ci n ( v ) p w m t sh ( v ) 4.7 4. 8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6 0.90 0.95 1.00 1.05 1.10 1.15 dsbl rising threshold vs. v cin smod rising threshold vs. v cin pwm rising threshold vs. v cin v ci n ( v ) dsbl t sh ( v ) 4.7 4. 8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 v ci n ( v ) smod t sh ( v ) 4.7 4. 8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 v ci n ( v ) p w m t sh ( v ) 4.7 4. 8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6 3.0 3.2 3.4 3.6 3. 8 4.0 4.2 4.4
vishay siliconix sic762cd document number: 65727 s10-0275-rev. a, 08-feb-10 www.vishay.com 11 electrical characteristics startup with v in ramping up v in = 12 v, v out = 1.2 v, f s = 500 khz enable with v in = 12 v, v out = 1.2 v, f s = 500 khz pwm start with v in = 12 v, v out = 1.2 v, f s = 500 khz v drv /v cin : 2 v/div v in : 5 v/div v o : 0.5 v/div t: 2 ms/div pwm: 3 v/div dsbl#: vswh: 5 v/div t: 20 s/div. 2 v/div v o : 0.5 v/div v drv /v cin : 2 v/div v in : 5 v/div v o : 0.5 v/div t: 50 s/div pwm: 3 v/div power off with v in ramping down v in = 12 v, v out = 1.2 v, f s = 500 khz disable with v in = 12 v, v out = 1.2 v, f s = 500 khz pwm turn-off with v in = 12 v, v out = 1.2 v, f s = 500 khz v drv /v cin : 2 v/div v o : 0.5 v/div pwm: 3 v/div t: 20 ms/div vswh: 5 v/div dsbl#: 2 v/div v o : 0.5 v/div t: 0.5 ms/div v drv /v cin : 2 v/div v in : 5 v/div v o : 0.5 v/div t: 500 s/div pwm: 3 v/div
www.vishay.com 12 document number: 65727 s10-0275-rev. a, 08-feb-10 vishay siliconix sic762cd electrical characteristics startup with v drv /v cin ramping up v in = 12 v, v out = 1.2 v, f s = 500 khz switching waveforms with smod enabled v in = 12 v, v out = 1.2 v, f s = 500 khz, i out = 1.5 a switching waveforms at pwm rising edge v in = 12 v, v out = 1.2 v, f s = 500 khz, i out = 0 a v drv /v cin : 2 v/div v in : 5 v/div v o : 0.5 v/div t: 2 ms/div pwm: 3 v/div gl: 5 v/div vswh: 8 v/div t: 0.5 s/div. gh: 10 v/div i l : 4 a/div pwm: 2 v/div gl: 2 v/div gh: 5 v/div vswh: 5 v/div t: 10 ns/div. power off with v drv /v cin ramping down v in = 12 v, v out = 1.2 v, f s = 500 khz switching waveforms with smod disabled v in = 12 v, v out = 1.2 v, f s = 500 khz, i out = 4 a switching waveforms at pwm falling edge v in = 12 v, v out = 1.2 v, f s = 500 khz, i out = 0 a v drv /v cin : 2 v/div v o : 0.5 v/div pwm: 3 v/div t: 10 ms/div v in : 5 v/div gl: 5 v/div vswh: 8 v/div t: 0.5 s/div. gh: 10 v/div i l : 4 a/div t: 10 ns/div pwm: 2 v/div gl: 2 v/div gh: 5 v/div vswh: 5 v/div
vishay siliconix sic762cd document number: 65727 s10-0275-rev. a, 08-feb-10 www.vishay.com 13 electrical characteristics switching waveforms at pwm rising edge v in = 12 v, v out = 1.2 v, f s = 500 khz, i out = 30 a pwm: 2 v/div gl: 2 v/div gh: 5 v/div vswh: 5 v/div t: 20 ns/div. switching waveforms at pwm falling edge v in = 12 v, v out = 1.2 v, f s = 500 khz, i out = 30 a pwm: 2 v/div gl: 2 v/div gh: 5 v/div vswh: 5 v/div t: 10 ns/div.
www.vishay.com 14 document number: 65727 s10-0275-rev. a, 08-feb-10 vishay siliconix sic762cd typical system efficiency with sic762cd v in = 12 v and 19.5 v, v out = 1.2 v, v drv = v cin = 5 v; no air flow ihlp5050fderr33m01 inductor l = 330 nh, der = 0.83 m typical system power loss with sic762cd v in = 12 v and 19.5 v, v out = 1.2 v, v drv = v cin = 5 v; no air flow ihlp5050fderr33m01 inductor l = 330 nh, der = 0.83 m 76 7 8 8 0 8 2 8 4 8 6 88 90 92 0 3 6 9 12 15 1 8 21 24 27 30 33 efficiency ( % ) load c u rrent (a) 300 khz 400 khz 500 khz v i n = 12 v , v out = 1.2 v 76 7 8 8 0 8 2 8 4 8 6 88 90 92 0 3 6 9 12 15 1 8 21 24 27 30 33 efficiency ( % ) load c u rrent (a) 400 khz 300 khz 500 khz v i n = 19.5 v , v out = 1.2 v figure 6 - system efficiency with sic762 po w er loss ( w ) load c u rrent (a) 0 2 4 6 8 10 12 0 3 6 9 12 15 1 8 21 24 27 30 33 v i n = 12 v , v out = 1.2 v 400 khz 300 khz 500 khz po w er loss ( w ) load c u rrent (a) 0 2 4 6 8 10 12 0 3 6 9 12 15 1 8 21 24 27 30 33 v i n = 19.5 v , v out = 1.2 v 500 khz 400 khz 300 khz figure 7 - system power loss with sic762
vishay siliconix sic762cd document number: 65727 s10-0275-rev. a, 08-feb-10 www.vishay.com 15 package dimensions notes: 1. use millimeters as the primary measurement. 2. dimensioning and tolerances conform to asme y14.5m-1994. 3. n is the number of terminals. nd is the number of terminals in x-direction and ne is the number of terminals in y-direction . 4. dimension b applies to plated terminal and is m easured between 0.20 mm and 0.25 mm from terminal tip. 5. the pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body . 6. exact shape and size of th is feature is optional. 7. package warpage max. 0.08 mm. 8. applied only for terminals. dim millimeters inches min. nom. max. min. nom. max. a (8) 0.70 0.75 0.80 0.027 0.029 0.031 a1 0.00 - 0.05 0.000 - 0.002 a2 0.20 ref. 0.008 ref. b (4) 0.20 0.25 0.30 0.078 0.098 0.011 d 6.00 bsc 0.236 bsc e 0.50 bsc 0.019 bsc e 6.00 bsc 0.236 bsc l 0.35 0.40 0.45 0.013 0.015 0.017 n (3) 40 40 nd (3) 10 10 ne (3) 10 10 d2-1 1.45 1.50 1.55 0.057 0.059 0.061 d2-2 1.45 1.50 1.55 0.057 0.059 0.061 d2-3 2.35 2.40 2.45 0.095 0.094 0.096 e2-1 4.35 4.40 4.45 0.171 0.173 0.175 e2-2 1.95 2.00 2.05 0.076 0.078 0.080 e2-3 1.95 2.00 2.05 0.076 0.078 0.080 k1 0.73 bsc 0.028 bsc k2 0.21 bsc 0.008 bsc figure 8 - powerpak mlp 66-40 40 1 2 x 2 x pin 1 dot b y marking mlp66-40 (6 mm x 6 mm) 10 11 20 21 30 31 56 4 top v ie w bottom v ie w side v ie w a b c d 0.10 c b e 0.10 c a a 0.0 8 c a1 a2 0.41 k2 k1 d2-1 pin #1 dent e2-1 e d2-3 d2-2 e2-3 e2-2 ( n d-1)x e ref. ( n d-1)x e ref. 0.10 m c a b
www.vishay.com 16 document number: 65727 s10-0275-rev. a, 08-feb-10 vishay siliconix sic762cd land pattern dimensions tape and reel carrier tape dimensions notes: 1. 10 sprocket hole pitch cumulative tolerance 0.2. 2. camber in compliance with eia 481. 3. pocket position relative to sprocket hole m easured as true position of pocket, not pocket hole. vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?65727 . figure 9 - powerpak mlp 66-40 1 1 0.025 0.100 0.100 0.100 0.100 0.025 40 0.100 0.100 0.100 0.100 0.100 0.100 0.600 2.600 1.700 0.320 0.310 40 2.200 2.200 0.276 0.276 0.200 4.600 figure 10 - powerpak mlp 66-40 12.00 1.75 0.1 0.25 0.30 0.05 b o section a-a a o = 6.30 b o = 6.30 k o = 1.10 ? 1.5 + 0.1 - 0.0 a o k o r 0.3 max. ? 1.50 min. r 0.25 2.00 0.10 see note 3 4.00 see note 1 a a 16.0 0.3 7.5 0.1 see note 3
document number: 64846 www.vishay.com 04-may-09 1 package information vishay siliconix powerpak ? mlp66-40 case outline notes 1. use millimeters as the primary measurement 2. dimensioning and tolerances conform to asme y14.5m. - 1994 3. n is the number of terminals. nd is the number of terminals in x-direction and ne is the number of terminals in y-direction 4. dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip 5. the pin #1 identifier must be existed on the top surface of the package by using indentation ma rk or other feature of packag e body 6. exact shape and size of this feature is optional 7. package warpage max. 0.08 mm 8. applied only for terminals 40 1 2 x 2 x pin 1 dot b y marking mlp66-40 (6 mm x 6 mm) 10 11 20 21 30 31 56 4 top v ie w bottom v ie w side v ie w a b c d 0.10 c b e 0.10 c a a 0.0 8 c a1 a2 0.41 k2 k1 d2-1 pin #1 dent e2-1 e d2-3 d2-2 e2-3 e2-2 ( n d-1)x e ref. ( n d-1)x e ref. 0.10 m c a b dim. millimeters inches min. nom. max. min. nom. max. a (8) 0.70 0.75 0.80 0.027 0.029 0.031 a1 0.00 - 0.05 0.000 - 0.002 a2 0.20 ref. 0.008 ref. b (4) 0.20 0.25 0.30 0.078 0.098 0.011 d 6.00 bsc 0.236 bsc e 0.50 bsc 0.019 bsc e 6.00 bsc 0.236 bsc l 0.35 0.40 0.45 0.013 0.015 0.017 n (3) 40 40 nd (3) 10 10 ne (3) 10 10 d2-1 1.45 1.50 1.55 0.057 0.059 0.061 d2-2 1.45 1.50 1.55 0.057 0.059 0.061 d2-3 2.35 2.40 2.45 0.095 0.094 0.096 e2-1 4.35 4.40 4.45 0.171 0.173 0.175 e2-2 1.95 2.00 2.05 0.076 0.078 0.080 e2-3 1.95 2.00 2.05 0.076 0.078 0.080 k1 0.73 bsc 0.028 bsc k2 0.21 bsc 0.008 bsc ecn: t09-0195-rev. a, 04-may-09 dwg: 5986
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

▲Up To Search▲

Price & Availability of SIC762CD-T1-GE3

	To Download SIC762CD-T1-GE3 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .